The present invention relates to a chip capacitor and wiring in an integrated circuit and to a machine readable medium embodying a design structure and, more specifically, to a metal insulator metal capacitor and interconnecting wiring containing vias connecting to other wiring levels.
The top and bottom electrodes of a metal insulator metal (MIM) parallel plate capacitor may be contacted using vias from the top and bottom electrodes to the wiring layer above the capacitor which is cumbersome and results in excessive radio frequency (rf) coupling noise.